1. Technical Field of the Invention
The present invention relates to a digital-to-analog converter.
2. Description of Related Art
In many circuit systems in which a digital input code has to be converted into an analog output quantity it is essential that the conversion be monotonic, that is to say, such that an increase or a reduction of the digital input code corresponds to, respectively, an increase or a reduction of the analog output quantity. In applications to portable equipment such as cell-phones, moreover, the consumption of electric energy has to be reduced to the greatest possible extent. This need is felt, for example, in the design of the converter used in the feedback circuit for controlling the frequency of the quartz oscillator that determines the clock of the system. Since this circuit is always active, a low consumption of the digital-to-analog (D/A) converter is particularly desirable.
A schematic representation of a D/A converter commonly used for this purpose is shown in FIG. 1. A resistive network, in this example a resistive divider made up of a multiplicity of resistors R (212−1=4095 in this particular example), all of equal resistance R and arranged in series with each other, is connected on the one hand through a transistor M1, in this example a P-channel MOSFET, to the positive terminal Vdd of a supply source, and on the other through a further transistor RL to the negative terminal (ground) of the supply source. The gate terminal of the transistor M1 is connected to the output of an operational amplifier OPA1, which has an inverting input connected to a reference voltage source Vref and a non-inverting input connected to the connection node N1 between the resistive divider and the drain terminal of the transistor M1. The divider taps (which number 212=4096 in this example) are each connected to a terminal of an electronic switch (SW0-SW4095) that has its other terminal connected, in a common node N4, to a non-inverting input terminal of a second operational amplifier OPA2 so as to apply to it a voltage Vin that corresponds to the digital code from time to time associated with the closed electronic switch.
As far as the functioning is concerned, due to the effect of the feedback connection between the node N1 and the non-inverting input of the amplifier OPA1, the current I that passes the resistive divider is regulated in such a way as to maintain the node N1 at a voltage equal to the reference voltage Vref. The voltage Vin applied as input to the amplifier OPA2 can assume 4096 discrete values in voltage steps of ΔV1=I*R, where R is the resistance of each of the resistors indicated by the same symbol between Vref and a minimum voltage determined by the resistance of the resistor RL, by means of the selective closure of the switches SW0-SW4095. Each of these discrete values represents the analog value corresponding to the digital code that determines the closure of the corresponding electronic switch. The voltage Vin is amplified by the operational amplifier OPA2 with a gain determined by the resistors R1 and R2. The voltage at the amplifier output, which is also the output of the converter, will be Vout=Vin*(1+R1/R2), where R1 and R2 are the resistances of the resistors indicated by the same symbol in FIG. 1.
The D/A converter described above is characterized by an intrinsic monotonicity, because the divider voltage that from time to time is applied to the input of the amplifier OPA2 increases/decreases as the digital code to be converted increases/decreases and is therefore suitable for being employed in the systems cited at the beginning. Furthermore, the gain of the converter can be regulated at will by means of resistors (R1 and R2) that are not in any way related with the resistors of the resistive divider, so that they can be chosen to have a relatively high value and thus reduce the electricity consumption to a minimum. In an integrated circuit, nevertheless, the formation of this converter calls for the occupation of an extensive area on account of the large number of resistors. These resistors, moreover, cannot be realized as normal polysilicon resistors when the divider is made up of a large number of resistors. Indeed, the maximum number of resistors is limited by an overall resistance of the divider that makes the current crossing the divider become so small as to make it comparable with the leakage current of the diffused regions of the transistors that perform the function of electronic switches. In this case, moreover, even the conversion time becomes unacceptably long. In order to overcome this limit the resistors are formed by means of a technique that utilizes a special low-resistivity silicon; however, the resistors produced by the use of this technique are often of far from uniform value, so that the production yield of the integrated circuit is low.
Another known converter is shown in FIG. 2. It is made up of two sections, a first section for the conversion of the digital code with the more significant bits (MSB) and a second section for the conversion of the part of the digital code with the less significant bits (LSB). The first section, indicated overall by MSB, has a structure identical to that of the converter of FIG. 1, but in this example has only 29−1=511 resistors, all having the same resistance R, and 29=512 electronic switches SW0-SW511 controlled by a 9-bit decoding logic (DEC-9BIT). The second section, indicated overall by LSB, is made up of as many current generators (MD0, MD1, MD2) as there are bits considered to be less significant in the code that is to be converted, in this example three bits (D0, D1, D2). The three generators MD0, MD1, MD2 consist of N-channel MOS transistors that can be selectively connected by means of three electronic selectors SD0, SD1 and SD2 controlled by a 3-bit transcoding logic (TRANSCOD-3BIT) between the terminals (Vdd and ground) of the supply source or between the inverting input of an operational amplifier OPA2 (equal to the one of the converter of FIG. 1) and ground. The three transistors MD0-MD2 are connected in current mirror fashion to a diode-connected N-channel MOS transistor M3. The transistor M3 is connected in series to a P-channel MOS transistor M2 between the terminals of the supply source (Vdd, ground). The gate terminal of the transistor M2 is connected to the gate terminal of the transistor M1, which stabilizes the voltage applied to the resistive divider, so that the current I of the divider is mirrored in the circuit branch containing M2 and M3. The sizes of the transistors M1, M2, M3, MD0-MD2 are chosen in such a way that the generators formed by the transistors MD0-MD2 are presented in binary form, that is to say, the currents that pass through them are equal to, respectively 20*I/4, 21*I/4 and 22*I/4, and they therefore contribute to the formation of the converter output voltage Vout in the right proportion to represent the three less significant bits of the code to be converted. In the example here presented M1 and M2 are of the same size, for example, they are formed by a single (n=1), M3 and MD2 are likewise of the same size, for example, they are formed by (n=4), MD1 has half the size of MD2, for example, it is formed by two (n=2) and MD0 has half the size of MD1, for example, it is formed by (n=1).
The output voltage of the converter isVout=Vin*(1+R1′/R2′)+IL*R1′where R1′ and R2′ are the resistances of the resistors indicated by the same symbol in the figure and IL is the current that the generators MD0-MD2 inject into the connection node N2 between the resistors R1′ and R2′, i.e., into the inverting input terminal of the operational amplifier OPA2.
If we put R1′=R2′, the gain of the amplifier OPA2 will be g=1+R1′/R2′=2, so that the contribution of the MSB section to the output of the operational amplifier OPA2 will be Vin*2 and, more particularly, the contribution made by a resistor R to the output Vout will be ΔV1*2=I*R*2. If we put R1′=R, the contribution of the LSB section will be at the most equal to ⅞ of the contribution made to the output by a resistor R of the divider. In fact, if only the generator MD0 is connected to the node N2 (i.e., the selector SD0 is in the position in which the drain terminal of the transistor MD0 is connected to N2 and the selectors SD1 and SD2 are in the positions in which the drain terminals of the respective transistors MD1 and MD2 are connected to the terminal Vdd), the current IL will be ¼ of the current that passes through M3. Since the current of M3 is equal to the current of M1, i.e., equal to the current I that passes through the divider, the current injected into the node N2 will be IL=¼*I and therefore the contribution to the output Vout made by the LSB section of the converter will be equal to ⅛ of the contribution made to the output by a resistor R of the divider, because the feedback resistor R1′ of the amplifier OPA2 has the same resistance R. When all three generators MD0-MD2 of the LSB section finish their current to the amplifier OPA2, the current IL will amount to 7/4 of the current I that passes through the divider and the contribution to the output voltage will therefore amount to 7/4*I*R, i.e., ⅞ of the contribution of a resistor R of the divider. The contribution of the LSB section to the output voltage Vout will therefore be a voltage that varies in steps of ΔV2=½L*2*ΔV1, where L is the number of the less significant bits.
The converter of FIG. 2 has the advantage that, given parity of resolution, it can be integrated into a much smaller area than the converter of FIG. 1, this thanks to the fact that it has only one eighth the number of resistors of the divider of FIG. 1 and only a few extra transistors; it is, however, associated with some drawbacks that render its use rather problematic. More particularly, bearing in mind that the divider can be realized with equal resistors R having typical values comprised between 20 and 200 Ohms and that the operational amplifier OPA2 may have a gain typically comprised between 1.5 and 2.5, the resistors that determine the gain cannot be chosen with a high resistance, as is possible in the case of the converter of FIG. 1, because the feedback resistor R1′ must have a value equal to that of a resistor of the divider and R2′ cannot have a value much greater than R′, so that the consumption of the converter is unacceptably great. The consumption can be reduced by utilizing a feedback resistor R1′ of a larger value and using correspondingly smaller current generators MD0-MD2, so that the contribution of the LSB section to the voltage output of the converter remains unchanged. Nevertheless, if significant consumption reductions are to be obtained, the increase of the feedback resistance and the reduction of the generator current would have to be of such magnitude as to make it difficult, if not altogether impossible, to realize the generators in such a way as to maintain the correct ratio between the currents they produce. In any case, one would have to avoid the generator currents becoming so small as to be comparable with the leakage currents of the junctions of the MOS transistors of which the generators are made.
Another disadvantage of the converter shown in FIG. 2 consists of the fact that it does not have a great accuracy when a large excursion of the output voltage is needed. This is due to the fact that the current generators may be far removed from the operating conditions of an ideal generator. As is well known, if a transistor is to function in conditions close to those of an ideal generator, it would always have to work in the saturation zone, that is to say, its current would have to depend only on the gate voltage and not on the drain voltage. This will be the case when the source-drain voltage never drops below a predetermined minimum value, below which the transistor would be working in the linear zone. In the case of the converter of FIG. 2, the output voltage Vout may be very close to ground potential, so that when the drain terminals of the transistors MD0-MD2 are connected to the node N2, their voltages may be so low as to cause them to operate in the non-linear zone.
There is a need in the art for a D/A converter that can be integrated into a small area and has only a limited consumption.
There is also a need in the art for a D/A converter having great linearity and precision even at the maximum excursion of the output voltage.